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RTL Synthesis(Design Synthesis)培训课程
课程大纲：
第一阶段 Design Compiler 1
Unit 1
Introduction to Synthesis
Design and Technology Data
Design and Library Objects
Timing Constraints
Unit 2
Environmental Attributes
Synthesis Optimization Techniques
Timing Analysis
Unit 3
Additional Constraint Options
Multiple Clocks and Timing Exceptions
Congestion Analysis and Optimization
Post-Synthesis Output Data
Conclusion
第二阶段 Design Compiler 2: Low Power
Clock Gating
Leakage Power Optimization
Power Intent using IEEE 1801 UPF
Library Requirements
Synthesis with UPF
Power Aware DFT
第三阶段 DFT Compiler
Unit 1
Introduction to Scan Testing
DFT Compiler Flows and Setup
Test Protocol
DFT Design Rule Checks
Unit 2
DFT DRC GUI Debug
DRC Fixing
Top-Down Scan Insertion
Exporting Files
Unit 3
High Capacity DFT Flows
On-Chip Clocking (OCC)
Multi-Mode DFT
DFT MAX
